To increase the functionality and density of semiconductor devices multiple semiconductor chips are stacked on a substrate or on each other. For instance, chips with the same functions, e.g., memory chips are stacked to increase the memory density or chips with different functions, e.g., processor chip and memory chip are stacked to minimize the processing time. Usually a first chip is mounted on a substrate. This chip is connected to substrate either by bonding bumps using flip-chip technology or by wire bonding. A second chip is then mounted onto the upper side of the first chip. In case of flip-chip bonding the second chip is mounted directly on the back side of the first chip (with an interlaying adhesive tape) or in case of wire bonding with spacers arranged between the first and the second chip for preventing the bonding wires for any damaging. Usually the second chip is also connected to the substrate or to the first chip by wire bonding.
However, the chips are stacked at chip level, i.e., after dicing the chips. Therefore, the manufacturing process is made chip by chip with a low productivity. Sometimes chips after dicing are also called “die.” In this specification the term “chip” is used exclusively.
For increasing the productivity a stacking method for stacking chips at wafer level is known, wherein the wafers each having a plurality of semiconductor chips are stacked on each other. The wafers are prepared using any conventional semiconductor manufacturing process. Each semiconductor chip is provided with a plurality of through electrodes typically arranged in a peripheral region of the semiconductor chip and bumps are formed on at least one end surface of the through electrodes to be used as an interconnect element.
A plurality of such wafers are then sequentially stacked so that the corresponding through electrodes or bumps of adjacent semiconductor chips are aligned and brought into contact so as to provide electrical connection between vertical adjacent semiconductor chips. The stacked wafers are then divided into individual chip stack packages.
If the through electrodes are galvanically deposited in a hole through the silicon of the wafer it is necessary to generate a passivation on the inner surface of the through-hole in an additional manufacturing step.